1. Field of the Invention
The present invention relates to a DC/DC converter.
2. Description of the Related Art
Various kinds of electronic devices employ a DC/DC converter that converts a DC voltage having a given voltage value into a DC voltage having a different voltage value. In order to suppress ripple in the input current of the DC/DC converter, a multi-phase DC/DC converter is employed. FIG. 1 is a circuit diagram showing a multi-phase step-up (boost) DC/DC converter (which will simply be referred to as the “DC/DC converter”) 900. The DC/DC converter 900 receives a DC input voltage VIN via an input line 902, and generates a stepped-up voltage VOUT at an output line 904. The DC/DC converter 900 is configured as an M-channel (M represents an integer of 2 or more) DC/DC converter. Each channel of the DC/DC converter 900 includes a switching transistor M1, an inductor L1, and a rectifier element D1. The M channels have a common output capacitor C1. It should be noted that, in the present specification, the channel number is represented by an appended suffix as necessary.
A controller 910 includes a common error amplifier 912 for the M channels and peak current mode pulse modulators 914_1 through 914_M provided to the respective channels, and drivers 922_1 through 922_M provided to the respective channels. The output voltage VOUT is divided by means of resistors R11 and R12 so as to generate a feedback voltage VFB that corresponds to the output voltage VOUT. An error amplifier 912 amplifies the difference between the feedback signal VFB and a reference voltage VREF configured as a target value of the feedback signal VFB, so as to generate an error signal VERR that corresponds to the difference. The error signal VERR is supplied to the pulse modulators 914_1 through 914_M respectively provided to the multiple channels.
Each pulse modulator 914 includes a PWM (pulse width modulation) comparator 916, a logic circuit 918, and a slope compensator 920. A current sensing resistor R1 is provided in order to detect a current that flows through a corresponding switching transistor M1 in an on period of the switching transistor M1. Specifically, the current sensing resistor R1 generates a current detection signal VIS that indicates the current thus detected. The slope compensator 920 superimposes a slope signal VSLOPE on the current detection signal VIS. The PWM comparator 916 compares the current detection signal VIS with the error signal VERR. When the current detection signal VIS reaches the error signal VERR, the PWM comparator 916 asserts (sets to high level, for example) a reset signal (which will also be referred to as an “off signal”) ICMP. In response to the reset signal ICMP, the logic circuit 918 switches a PWM signal SPWM to an off level (low level, for example) which instructs the switching transistor M1 to turn off. Furthermore, in response to a PWM clock (which will also be referred to as the “set signal” or “on signal”) which is asserted for every predetermined period, the logic circuit 918 switches the PWM signal SPWM to an on level (high level, for example) which instructs the switching transistor M1 to turn on. The driver 922 drives the switching transistor M1 according to the PWM signal SPWM.
Known examples of such a multi-channel DC/DC converter include an arrangement in which the number of channels to be operated is adjusted according to the load current (output current) ILOAD (shedding converter). FIG. 2 is a shedding operation of the DC/DC converter shown in FIG. 1. For ease of understanding, description will be made below regarding an arrangement in which M=4, i.e., regarding a four-channel converter 900. A pair of threshold values ITH1 and ITH2 are defined for the DC/DC converter 900. When ILOAD<ITH1, only the first channel CH1 is enabled (set to an active state or operating state). When ITH1<ILOAD<ITH2, the first channel CH1 and the second channel CH2 are enabled. When ITH2<ILOAD, all the channels, i.e., the first channel CH1 through the fourth channel CH4 are enabled. A channel thus enabled will be referred to as an “enabled channel” hereafter. A channel thus disabled will be referred to as a “disabled channel” hereafter. FIG. 2 shows the operations of CH1 through CH4. In the drawing, the ideal coil current, i.e., the ideal switching duty ratio, of each channel is represented by a dashed line. The control operation as shown in FIG. 2 for switching between an enabled channel and a disabled channel in a logical manner will be referred to as “hard shedding”. Such hard shedding has an advantage of providing high responsivity. However, as a result of investigating such hard shedding, the present inventor has recognized that hard shedding has a problem of poor stability of the output voltage VOUT as described below.
FIG. 2 also shows the actual coil current (actual switching duty ratio) for each of the channels CH1 through CH4, which are each represented by a dashed line. At the time point t0, the operation is switched from the single-channel operation to the two-channel operation. The change in the error signal VERR is dull, as represented by the solid line, due to a response delay of the error amplifier 912. As a result, the first channel CH1 provides an amount of current having a waveform represented by the solid line. In this case, excess current, which is represented by the hatched area, occurs in the first channel CH1, which is supplied to the output capacitor C1.
Furthermore, the duty ratio of each channel is also determined according to the common error signal VERR. Accordingly, at the time point t0, the second channel CH2 supplies the same amount of current as that of the first channel CH1. This leads to a problem of supplying an amount of current larger than the ideal amount of current. That is to say, excess current, which is represented by the hatched area, also occurs in the channel CH2, which is also supplied to the output capacitor C1.
That is to say, when the load current ILOAD increases, the duty ratio of each channel becomes excessive. This leads to the generation of a surplus amount of coil current, leading to overshoot in the output voltage VOUT.
Conversely, when the load current ILOAD decreases, the duty ratio of each channel becomes too small. This leads to the generation of an insufficient amount of coil current, leading to undershoot in the output voltage VOUT. Such problems are not restricted to such a step-up DC/DC converter, but can occur in various kinds of converters such as step-down (Buck) DC/DC converters, step-up/step-down converters, etc.